1. Field of the Invention
This invention relates to testing of digital systems. In particular, this invention relates to in-circuit testing of digital systems.
2. Description of Related Art
Many in-circuit testing techniques have been proposed over the years. One such technique is the Level Sensitive Scan Design (LSSD) technique. Under LSSD, memory elements, such as registers or flip-flops, are serially connected to form a "scan-path," for scanning in test data and scanning out test results. At the integrated circuit level, a typical scan path begins at an input pin of the integrated circuit and ends at an output pin of the integrated circuit. Typically, a clock signal controls the shifting of data along the scan path. The test data, which is provided at the rate of one bit per clock cycle, allows the user to initialize the integrated circuit to a known state, to command the circuit to execute the functions under test, and to probe the resulting states of the circuit or resulting data for diagnostic purposes. An example of a test structure using the LSSD technique can be found in U.S. Pat. No. 4,488,259 by Brian R. Mercy, assigned to IBM Corporation entitled "On Chip Monitor", filed Oct. 29, 1982, issued Dec. 11, 1984.
As the complexity of digital systems grows, providing control to the test structure increases the flexibility of the test structure and increases control over in the scan path. One technique includes a command register in the test structure, in order to implement a set of commands to the test structure for greater control over the test sequence and test data flow. In such a test structure, in addition to the serial input pin, the serial output pin and the clock input pin, a command/data pin is provided to steer the serial input signal to either the command register or the data (scan) register and to steer the command or test data output signal to the serial output pin. Further, it is desirable to provide scan paths across chip boundaries. By providing scan paths across chip boundaries, not only can each chip be tested individually, the multi-chip digital system can tested as a whole.
Command and data multiplexing in the serial data input and the serial data output pins minimizes the number of dedicated pins used by the test structure. An example of such test structure is found in U.S. Pat. No. 4,710,927, by Michael J. Miller, filed Jul. 24, 1986 and issued Dec. 1, 1987.
However, multiplexing commands and test data on the same serial input and output pins is time-consuming and restricts the chips under test to be connected serially. Serial connections are inefficient because, if the same command is directed to each of the test structures in a scan path, the command must be repeated for each test structure, and the command for each test structure must scan through all preceding test structures in the scan path.